Clock gating is used in high performance semiconductor systems to reduce average active power by idling functional units and preventing wasteful events. This is disclosed, for example, in the article to N. Kurd, et al. entitled Multi-GHz Clocking Scheme for Intel® Pentium® 4 Microprocessor”, ISSCC Digest of Technical Papers, 2001, p. 404. However, with technology scaling, leakage power of idle units becomes a large fraction of the total chip power. As a result, the overall power savings achievable by clock gating alone is diminishing.
Dynamic MOSFET threshold voltage (Vt) control schemes to meet the opposing requirements of high-performance, during system functional units active periods, and low power, during system functional units idle periods, have been proposed. See, for example, co-assigned and co-pending U.S. application Ser. No. 10/639,942, filed Aug. 13, 2003, entitled “Device Threshold Control of Front-Gate Silicon-On-Insulator MOSFET using a Self-Aligned Back-Gate”; and the article to J. Tschang, et al., entitled “Dynamic-Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors”, ISSCC Digest of Technical Papers, 2003, p. 102.
In these prior art schemes, back-gated (SOI technology) or body node (bulk technology) MOSFETs are employed. By applying the proper bias to the nMOSFET back-gate or body node, its threshold voltage can be dynamically changed from low values (≦0 Volts), during system active periods for maximum performance, to high values (≧0.2 Volts) during system idle periods for minimum leakage power. For pMOSFETs, the opposite voltages are applicable.
The overall performance impact of these dynamic leakage control techniques on the system is dictated by the time required to switch the transistor back-gate or body node voltage during “idle” or “active” transitions. This time can be as large as several clock cycles. Also, for any of these dynamic leakage control techniques, to achieve reduction in the overall power, the leakage energy saved during the “idle” period must be larger than any energy overhead incurred during switching the transistor back-gates or body nodes between “idle” and “active” modes. The minimum “idle” time required to achieve overall power saving is dictated by the energy spent in switching the back-gate or body nodes and may account to several additional clock cycles.
It is an object of the present invention to provide a methodology in which the back-gates or body nodes of MOSFETs in a system or chip can be ‘statically’ biased for high performance and low standby power.